1. Field of the Invention
Embodiments of the present invention relate generally to nonvolatile memory devices and related methods of operation. More particularly, embodiments of the invention relate to nonvolatile memory devices and related programming methods.
2. Description of the Related Art
A variety of nonvolatile memory devices use resistance materials to store data. For example, Phase Change Random Access Memory (PRAM), Resistive RAM (RRAM), Ferroelectric RAM (FRAM), and Magnetic RAM (MRAM) all use resistance materials to store data. In contrast to other forms of memory such as dynamic random access memory (DRAM) and flash memory, which store data using charges, devices using resistance materials tend to store the data by physically modifying the resistance materials. For instance, a PRAM typically stores data using different states of a phase change material such as a chalcogenide alloy, a RRAM typically stores data using different resistance values of a variable resistance material, a FRAM typically stores data using a polarization phenomenon of a ferroelectric material, and a MRAM typically stores data using a resistance variation of a magnetic tunnel junction (MTJ) thin film in response to a magnetization state of a ferromagnetic material.
To illustrate one way that resistance materials can be used to store data, an exemplary PRAM will now be described in further detail. The phase change material in a PRAM, typically chalcogenide, is capable of stably transitioning between amorphous and crystalline phases. The amorphous and crystalline phases (or states) exhibit different resistance values used to distinguish different logic states of memory cells in the memory devices. In particular, the amorphous phase exhibits a relatively high resistance and the crystalline phase exhibits a relatively low resistance.
The PRAM uses the amorphous state to represent a logical “1” (or data “1”) and the crystalline state to represent a logical “0” (or data “0”). In a PRAM device, the crystalline state is referred to as a “set state” and the amorphous state is referred to as a “reset state”. Accordingly, a memory cell in a PRAM stores a logical “0” by setting a phase change material in the memory cell to the crystalline state, and the memory cell stores a logical “1” by setting the phase change material to the amorphous state. Various PRAM devices are disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase change material in a PRAM is converted to the amorphous state by heating the material to a first temperature above a predetermined melting temperature and then quickly cooling the material. The phase change material is converted to the crystalline state by heating the material at a second temperature lower than the melting temperature but above a crystallizing temperature for a sustained period of time. Accordingly, data is programmed to memory cells in a PRAM by converting the phase change material in memory cells of the PRAM between the amorphous and crystalline states using heating and cooling as described above.
The phase change material in a PRAM typically comprises a compound including germanium (Ge), antimony (Sb), and tellurium (Te), ie., a “GST” compound. The GST compound is well suited for a PRAM because it can quickly transition between the amorphous and crystalline states by heating and cooling. In addition to, or as an alternative for the GST compound, a variety of other compounds can be used in the phase change material. Examples of the other compounds include, but are not limited to, 2-element compounds such as GaSb, InSb, InSe, Sb2Te3, and GeTe, 3-element compounds such as GeSbTe, GaSeTe, InSbTe, SnSb2Te4, and InSbGe, or 4-element compounds such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and Te81Ge15Sb2S2.
The memory cells in a PRAM are called “phase change memory cells”. A phase change memory cell typically comprises a top electrode, a phase change material layer, a bottom electrode contact, a bottom electrode, and an access transistor. A read operation is performed on the phase change memory cell by measuring the resistance of the phase change material layer, and a program operation is performed on the phase change memory cell by heating and cooling the phase change material layer as described above.
In general, the program operation is carried out by applying an electrical “set” or “reset” pulse to the electrode to change the phase change material layer to the “set” or “reset” state. Typically, the time required to program data “0” to a memory cell is about five times the time required to program data “1” to the memory cell. For example, the time required to program data “0” may be about 600 ns, while the time required to program data “1” may be about 120 ns.
Unfortunately, conventional PRAM devices can receive several bits of input at the same time but are unable to simultaneously program the bits into corresponding memory cells. For example, a PRAM may receive 16 inputs through a plurality of pins, but the PRAM may not be able to simultaneously access 16 phase change memory cells. One reason for this shortcoming is that if a current of 1 mA is required to program one phase change memory cell, then a current of 16 mA would be required to simultaneously program 16 phase change memory cells. Moreover, if the efficiency of a driver circuit providing the current is 10%, then in reality, a current of 160 mA would be required to simultaneously program the 16 memory cells. However, conventional PRAM devices are generally not equipped to provide currents with such high magnitudes.
Since a program driver in a PRAM device can only provide a limited amount of current, a program operation of several phase change memory cells can be divided into several “division program operations” each requiring only a fraction of the total current required to program all of the several phase change memory cells. In each division program operation, a subset (i.e., a “division”) of memory cells among a larger group are programmed. For example, a group of sixteen phase change memory cells can be programmed by dividing the sixteen phase change memory cells into eight groups (i.e., divisions) of two and simultaneously programming the two memory cells in each group of two in eight successive division program operations.
To prevent unnecessary current consumption and programming failures, the PRAM device may also perform a verify read operation to verify the program status of each selected memory cell. To perform the verify read operation, program data to be programmed in the selected memory cells is stored in a temporary storage location such as a program buffer. Next, the program data is programmed into selected cells. Then, the data stored in the selected memory cells is read and compared with the program data stored in the temporary storage location. Where the data stored in the temporary storage location is different from the data stored in the selected memory cells, the verify read operation indicates a program failure. Otherwise, the verify read operation indicates a program success.
FIG. 1 is a conceptual timing chart illustrating a conventional method of operating a PRAM device that uses division program operations. For explanation purposes, it will be assumed that a program operation of the PRAM device programs 16 bits of data to 16 selected memory cells divided into eight pairs, or groups, using eight division program operations.
Referring to FIG. 1, data is programmed in the PRAM device using a plurality of program loops (L=1 through 11). Before each program loop begins, a verify read operation is performed to detect memory cells, among the selected memory cells, that have not been successfully programmed. Thereafter, a division program operation is performed on groups of memory cells where at least one memory cell has not been successfully programmed—referred to as “failed groups” (incidentally, individual memory cells that have not been successfully programmed will be referred to as “failed cells”). In the example of FIG. 1, eight division program operations {circle around (1)} through {circle around (8)} correspond to eight respective cell groups.
In a program operation, all eight groups of memory cells generally begin as failed groups. Accordingly, in the first program loop (L=1), a division program operation is typically executed for each of the eight groups. In the second program loop (L=2), assuming that the third and fourth groups have been successfully programmed, a division program operation is performed on all eight groups, except for the third and fourth groups. Similarly, in remaining program loops, fewer groups are programmed as more groups become successfully programmed.
Unfortunately, conventional processes such as that described above do not take into account the fact that different program times are required to program data “0” and data “1” to selected memory cells. As a result, the duration of each division program operation may be required to be as long as the duration of a set pulse used to program data “0” even if some memory cells corresponding to the division program operation will only be programmed with data “1”. Accordingly, the time required to perform program operations may be unnecessarily large.